Design of beol patterns to reduce the stresses on structures below chip bondpads
US7071559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Dec 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.