Mariette Awad
11Patents
2h-index
10Co-inventors
47Inventor score
Filing activity: Jul 16, 2004 → Nov 6, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7666712B2 | Design of BEOL patterns to reduce the stresses on structures below chip bondpads | Electricity | 3 | Active |
| US7595681B2 | Method and apparatus for compensating for variances of a buried resistor in an integrated circuit | Physics | 2 | Active |
| US7071559B2 | Design of beol patterns to reduce the stresses on structures below chip bondpads | Electricity | 2 | Expired |
| US7489038B2 | Design of BEOL patterns to reduce the stresses on structures below chip bondpads | Electricity | 1 | Active |
| US8341428B2 | System and method to protect computing systems | Physics | 1 | Active |
| US8424071B2 | Method and apparatus for secure and reliable computing | Physics | 0 | Active |
| US9043889B2 | Method and apparatus for secure and reliable computing | Physics | 0 | Active |
| US10210202B2 | Recognition of free-form gestures from orientation tracking of a handheld or wearable device | Physics | 0 | Active |
| US9811555B2 | Recognition of free-form gestures from orientation tracking of a handheld or wearable device | Physics | 0 | Active |
| US7886237B2 | Method of generating a functional design structure | Physics | 0 | Active |
| US7962322B2 | Design structure for compensating for variances of a buried resistor in an integrated circuit | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.