Adaptive defect based testing
US7073107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Jun 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing integrated circuits. Each of the integrated circuits is tested with a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated circuits to produce first test results associated with a first characteristic of the integrated circuits. The first test results are recorded with associated integrated circuit identification information. The integrated circuits are logically subdivided into bins based at least in part on the associated integrated circuit identification information. A defectivity value is calculated for each bin of subdivided integrated circuits based at least in part on the first test results recorded with the associated integrated circuit identification information. The integrated circuits within each of the bins are tested with a second test at a second level of testing at a succeeding testing step in the fabrication cycle of the integrated circuits to produce second test results associated with a second characteristic of the integrated circuits. The second characteristic is related to the first characteristic and the second level of testing is varied from bin to bin based at least in part on the defe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.