Method for clock synchronization validation in integrated circuit design
US7073146B2 · kind B2 · utility
27Cited by
11References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 30, 2003 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Aug 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.