Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
US7074662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Sep 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.