Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating material
US7074691B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 10, 2005 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jun 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.