Underfilling efficiency by modifying the substrate design of flip chips
US7075016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Sep 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate structure including a substrate with solder bumps on a main region and a peripheral region of a front side thereof; a solder mask is formed over the front side of the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern includes openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.