Clock generator circuit stabilized over temperature, process and power supply variations
US7075353B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jan 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit incorporates a sub-PTAT (proportional to absolute temperature) current source and a super-PTAT current source for generating bias currents for a voltage reference generator and charging currents for a voltage ramp generator. The clock generator circuit further includes a linear comparator coupled to receive one or more switching voltage reference signals and a voltage ramp signal and generate a switching output signal as the clock signal. The clock signal is coupled to a clock decoder to generate the desired clock signals having the desired phase. The functional blocks of the clock generator circuit of the present invention operate together to generate a highly frequency stable clock signal. In one embodiment, the linear comparator incorporates a dual-differential-input (dual-channel) instrumentation amplifier as the comparator input stage to generate clock signals having clock frequency errors that are minimized over process, temperature and power supply variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.