Selectable multi-performance configuration
US7075542B1 · kind B1 · utility
44Cited by
6References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Dec 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a selectable multi-performance configuration. Instead of the traditional methods of producing separate high-end and low-end graphics chips, the present invention produces processing systems in a single unit. The single unit is readily and functionally partitionable. Each partition is capable of independent operation. By using all of the partitions a high-end graphics processing system may be simulated and tested. By using a subset of the partitions, a low-end graphics processing system may be simulated on the same system without the added cost of re-design of either hardware or software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.