Semiconductor memory device having optimum refresh cycle according to temperature variation
US7075847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Aug 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for controlling a refresh cycle in a semiconductor memory device includes a temperature detection controller for generating a detection control signal and a converting control signal; a temperature detection block, which is enabled by the detection control signal, for generating an analog detection voltage in response to a temperature variation; an analog to digital converter, which is enabled by the converting control signal, for converting the analog detection voltage into a digital control code; and a refresh controller for generating a refresh cycle control signal based on the digital control code in order to control the refresh cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.