Semiconductor memory device of hierarchy word type and sub word driver circuit
US7075852B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Oct 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, a first NMOS transistor and a first PMOS transistor are connected in series. A second NMOS transistor is connected with a node between the first PMOS transistor and the first NMOS transistor. The source of the first PMOS transistor is connected with a sub word line inverted signal obtained by inverting the sub word line signal, and the source of the first NMOS transistor is connected with a first negative voltage. A single main word line signal is connected to a gate of the first PMOS transistor and a gate of the first NMOS transistor, and the sub word line signal is connected with a gate of the second NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.