Apparatus for latency specific duty cycle correction
US7075856B2 · kind B2 · utility
8Cited by
8References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2005 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | May 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The illustrated embodiments relate to a control circuit that is adapted to use a latency signal to generate an output signal. The latency is adapted to be used to create a control signal that is dependent on the latency signal. The control signal is adapted to be used to select from among multiple input sources. The selected input source is adapted to be used to create an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.