Method and apparatus for interconnecting portions of circuitry within a data processing system
US7076584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2003 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jul 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for interconnecting circuit portions (12, 14, 16, 18, 20) within a data processing system (10) using a master/slave interfaces (30–37, 134) which may be configured by way of configuration registers (21–28, 156, 100). External address generation circuitry (140) and internal address generation circuitry (142) may be used to generate externally used addresses and internally used addresses, respectively. A circuit portion (e.g. 20) may have a plurality of interfaces (37, 134) which may operate as a slave interface (e.g. 134) or as a master interface (e.g. 37). A same master/slave interface structure and protocol (e.g. 30, 140, 142, 144, 28, 152) may be duplicated and individually configured to be used to communicate among all of the circuit portions (12, 14, 16, 18, 20) within a data processing system (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.