Memory controllers with interleaved mirrored memory modes
US7076618B2 · kind B2 · utility
5Cited by
25References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jul 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.