Processor with demand-driven clock throttling power reduction
US7076681B2 · kind B2 · utility
18Cited by
10References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jun 10, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.