Synchronous pipeline with normally transparent pipeline stages
US7076682B2 · kind B2 · utility
24Cited by
2References
37Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 4, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | May 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous pipeline segment and an integrated circuit (IC) including the segment. The segment includes an input stage, an output stage and at least one intermediate stage. A place holder latch associated with each stage indicates whether valid stage data is in the stage. A local clock buffer provides a local clock gating a corresponding stage. The input and output stages are normally opaque and intermediate stages are normally transparent. Data items pass locally asynchronously between the input and output stages and are separated by opaque gated intermediate stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.