High-pressure processing chamber for a semiconductor wafer
US7077917B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jul 4, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S134/902
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processing chamber having an improved sealing means is disclosed. The processing chamber comprises a lower element, an upper element, and a sealing means that tightly holds the lower element to the upper element to define a processing volume that is maintained using the minimum pressure necessary. The processing chamber comprises a plate having a first face that forms the processing volume and a second, opposing face that forms a seal-energizing cavity. In one embodiment, a surface area of the first face is smaller than a surface area of the second face. When the same pressure is applied against both the first face and the second face, the force on the second face is greater than the force on the first face, resulting in a sealing force exceeding a processing force generated within the processing volume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.