Vertical replacement-gate silicon-on-insulator transistor

US7078280B2 · kind B2 · utility

Assignee

• Agere Systems Inc. · US

Inventors

• Samir Chaudhry · Orlando, US
• Paul Arthur Layman · Schreiber, CA
• John Russell McMacken · Orlando, US
• J. Ross Thomson · Clermont, US
• Jack Qingsheng Zhao · Orefield, US

Key dates

• Filing date: Feb 6, 2004
• Grant date: Jul 18, 2006
• Expiry date: Apr 1, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a relatively thin vertical layer of single crystalline material. A MOSFET gate region, including a channel and a gate electrode, is formed over the first source/d…