Silicon-on-nothing fabrication process
US7078298B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jun 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to fabricate a silicon-on-nothing device on a silicon substrate is provided. The disclosed silicon-on-nothing device is fabricated on an isolated floating silicon active area, thus completely isolated from the silicon substrate by an air gap. The isolated floating silicon active area is fabricated on a silicon germanium layer with a surrounding isolation trench. A plurality of anchors is then fabricated to anchor the silicon active area to the silicon substrate before selectively etching the silicon germanium layer to form the air gap. Isolation trench fill and planarization complete the formation of the isolated floating silicon active area. The silicon-on-nothing device on the isolated floating silicon active area can be polysilicon gate or metal gate and with or without raised source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.