Method for eliminating inverse narrow width effects in the fabrication of DRAM device
US7078315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Nov 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer into the semiconductor substrate, thereby forming a doped region at the periphery of the active area in a channel width direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.