Transistor emitter having alternating undoped and doped layers
US7078744B1 · kind B1 · utility
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8Claims
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Key dates
| Filing date | Jul 10, 2004 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Feb 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/133
Abstract
A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, the steps of conformally depositing an undoped polysilicon layer and non-conformally depositing a doped polysilicon layer are repeated until the emitter window opening is filled. The method can further comprise a step of activating dopants. In another embodiment, an emitter structure is fabricated according to the above method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.