Analog delay locked loop having duty cycle correction circuit
US7078949B2 · kind B2 · utility
25Cited by
18References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Apr 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.