System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
US7078951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2004 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Sep 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.