Semiconductor device
US7079443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Mar 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.