Expanded comparator for control of digital delay lines in a delay locked loop or phase locked loop
US7079615B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Dec 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00065
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital delay locked loop (DLL) includes a phase detector that measures the phase difference between a signal to be synchronized and a reference signal. The phase detector produces an increase or decrease signal in response to the phase difference between the two signals. This signal is received by a binary counter, which changes its count in response. The output of the binary counter is supplied to a comparator logic that implements a thermometer coding scheme. Each of the comparator output signals enables or disables a corresponding transistor stack in a delay line, thereby changing the delay of the signal propagating through the delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.