Gold code generator design
US7080107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2004 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jul 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A gold code generator is described comprising two pairs of linear feedback shift registers, the seed values for the second pair of linear feedback shift registers are different from the seed values for the first pair of linear feedback shift registers. The second seed values are calculated from the first seed values. The use of this second pair of linear feedback shift registers prevents the need to use a wide span of taps to the linear feedback shift register to produce output bits. By using two pairs of linear feedback shift registers, a parallel output implementation can be produced in which multiple output bits are produced in a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.