Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains
US7080269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Aug 15, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.