Patent · US Expired

Methods for modeling latch transparency

US7080335B2 · kind B2 · utility

1Cited by

1References

15Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Erwin Behnen · Holzgerlingen, DE
Jeffrey P. Soreff · Poughkeepsie, US
James D. Warnock · Somers, US
Dieter Wendel · Schenefeld, DE

Key dates

Filing date	Sep 26, 2003
Grant date	Jul 18, 2006
Priority date	—
Expiry date	Sep 26, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.