Semiconductor devices having dual capping layer patterns and methods of manufacturing the same
US7081389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2004 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Mar 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.