Method for fabricating a gate structure of a FET and gate structure of a FET

US7081392B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gerhard Enders · Glen Allen, US
• Peter Voigt · Hallbergmoos, DE

Key dates

• Filing date: Jul 23, 2004
• Grant date: Jul 25, 2006
• Expiry date: Jul 23, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/667

Abstract

A method for fabricating a gate structure of a FET, having: (a) deposition and patterning of a sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section; (b) implantation of a channel doping into the gate section; (c) deposition and patterning of spacers at the sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers; (d) introduction of a mask material into the gate section that is not covered by the spacers; (e) removal of the spacers selectively with respect to the sacrificial layer sequence and mask material); (f) implantation of a halo doping in regions uncovered by the removed spacers; (g) removal of the mask material; (h) formation of a gate on the gate section; and (j) removal of the sacrificial layer sequence selectively with respect to the gate.