Manufacturing method for electronic device and multiple layer circuits thereof
US7081417B2 · kind B2 · utility
5Cited by
1References
11Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 24, 2004 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Nov 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.