Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism
US7082516B1 · kind B1 · utility
2Cited by
10References
12Claims
0Family size
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Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Jun 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.