Method and apparatus for mirroring units within a processor
US7082550B2 · kind B2 · utility
0Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2003 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Aug 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.