Inventor · Poughkeepsie, NY, US

Michael Billeci

24Patents
4h-index
35Co-inventors
59Inventor score

Filing activity: May 12, 2003 → Aug 23, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US7805634B2 Error accumulation register, error accumulation method, and error accumulation system Physics 44 Active
US7111196B2 System and method for providing processor recovery in a multi-core system Physics 14 Expired
US8683180B2 Intermediate register mapper Physics 6 Active
US7278063B2 Method and system for performing a hardware trace Physics 5 Expired
US9507602B2 Sharing program interrupt logic in a multithreaded processor Physics 4 Active
US8453124B2 Collecting computer processor instrumentation data Physics 3 Active
US8209668B2 Method and system for measuring the performance of a computer system on a per logical partition basis Physics 2 Active
US7146520B2 Method and apparatus for controlling clocks in a processor with mirrored units Physics 2 Expired
US8201067B2 Processor error checking for instruction data Physics 1 Active
US7480833B2 Method and system for performing a hardware trace Physics 1 Active
US9720764B2 Uncorrectable memory errors in pipelined CPUs Physics 1 Active
US7971034B2 Reduced overhead address mode change management in a pipelined, recycling microprocessor Physics 1 Active
US9665376B2 Sharing program interrupt logic in a multithreaded processor Physics 0 Active
US7380077B2 System, method and storage medium for controlling asynchronous updates to a register Physics 0 Active
US9075600B2 Program status word dependency handling in an out of order microprocessor design Physics 0 Active
US7814374B2 System and method for the capture and preservation of intermediate error state data Physics 0 Active
US9323640B2 Method and system for measuring the performance of a computer system on a per logical partition basis Physics 0 Active
US7225305B2 System, method and storage medium for controlling asynchronous updates to a register Physics 0 Expired
US7082550B2 Method and apparatus for mirroring units within a processor Physics 0 Expired
US9454377B2 Speculative branch handling for transaction abort Physics 0 Active
US9619237B2 Speculative branch handling for transaction abort Physics 0 Active
US8516228B2 Supporting partial recycle in a pipelined microprocessor Physics 0 Active
US9792124B2 Speculative branch handling for transaction abort Physics 0 Active
US7889569B2 System, method and storage medium for controlling asynchronous updates to a register Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.