Reducing clock skew in clock gating circuits
US7082582B1 · kind B1 · utility
9Cited by
9References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2003 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | May 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention includes a technique for a gated clock conversion for a circuit which includes a gating circuit and a sequential element. The gating circuit has a gated clock net that drives a clock input of the sequential element. The sequential element receives a first input net at a data input and generates an output net. The gating circuit has a user-defined clock net. The technique includes determining the gating circuit and transforming the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.