Method of generating a schematic driven layout for a hierarchical integrated circuit design
US7082589B2 · kind B2 · utility
5Cited by
4References
4Claims
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Key dates
| Filing date | Nov 10, 2003 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Aug 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a schematic driven layout for an integrated circuit design includes steps of: (a) receiving as input a representation of a integrated circuit design comprising a hierarchy of blocks; (b) selecting a block in the hierarchy of blocks that requires a physical design and that contains no missing components; (c) generating a physical design for the selected block so that the selected block is no longer a missing component of any other block; and (d) repeating steps (b) and (c) until a physical design has been generated for each block in the hierarchy of blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.