Fabrication and assembly structures and methods for memory devices
US7084007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Oct 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells. The fold line is formed by removal of some of the material, such as by perforations or depressions, by deforming the material, such as by creasing, or by altering a property of the material, such as by changing the strength or flexibility of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.