Integrated circuits with reduced interconnect overhead
US7084664B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17784
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits are provided that use on-chip data compression and decompression to minimize consumption of interconnect resources. Parallel-to-serial converter circuitry can use time-division multiplexing techniques to compress data. The compressed data may be conveyed between circuit blocks on the integrated circuit using a reduced number of parallel interconnect conductors. After the compressed data has been conveyed to its destination, a serial-to-parallel converter may use time-division demultiplexing techniques to decompress the data. Interconnect resources may be shared by dedicated circuits. With this arrangement, signals can be selectively steered through the appropriate dedicated circuitry to either maximize performance or to use compression and decompression to minimize interconnect resource consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.