System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
US7084686B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jun 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.