Clock-synchronous semiconductor memory device
US7085193B2 · kind B2 · utility
0Cited by
29References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 12, 2005 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Oct 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.