Coherency management for a “switchless” distributed shared memory computer system
US7085898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Apr 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses. Overall system coherency is maintained through the use of a dual token based scheme which provide coherency points to permit multiple non-contending requests for the same data un…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.