Inventor · Wappingers Falls, NY, US

Michael A. Blake

59Patents
11h-index
47Co-inventors
78Inventor score

Filing activity: Aug 15, 1996 → Apr 4, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US6038651A SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum Physics 124 Expired
US5752264A Computer architecture incorporating processor clusters and hierarchical cache memories Physics 85 Expired
US7111130B2 Coherency management for a “switchless” distributed shared memory computer system Physics 67 Expired
US6738872B2 Clustered computer system with deadlock avoidance Physics 38 Expired
US6738870B2 High speed remote storage controller Physics 36 Expired
US6988173B2 Bus protocol for a switchless distributed shared memory computer system Physics 32 Expired
US6738871B2 Method for deadlock avoidance in a cluster environment Physics 23 Expired
US7085897B2 Memory management for a symmetric multiprocessor computer system Physics 19 Expired
US6151655A Computer system deadlock request resolution using timed pulses Physics 17 Expired
US7085898B2 Coherency management for a “switchless” distributed shared memory computer system Physics 17 Expired
US6073182A Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic Physics 15 Expired
US8250308B2 Cache coherency protocol with built in avoidance for conflicting responses Physics 6 Active
US8423736B2 Maintaining cache coherence in a multi-node, symmetric multiprocessing computer Physics 6 Active
US8918587B2 Multilevel cache hierarchy for finding a cache line on a remote node Physics 5 Active
US9244851B2 Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index Physics 5 Active
US7934059B2 Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching Physics 5 Active
US8762651B2 Maintaining cache coherence in a multi-node, symmetric multiprocessing computer Physics 4 Active
US9507660B2 Eliminate corrupted portions of cache during runtime Physics 4 Active
US10339064B2 Hot cache line arbitration Physics 4 Active
US9703661B2 Eliminate corrupted portions of cache during runtime Physics 3 Active
US10489294B2 Hot cache line fairness arbitration in distributed modular SMP system Physics 3 Active
US10628313B2 Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache Physics 3 Active
US8364904B2 Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer Physics 3 Active
US10915461B2 Multilevel cache eviction management Physics 2 Active
US10628314B2 Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.