Incremental netlisting
US7086030B1 · kind B1 · utility
4Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Oct 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for preparing a design in a high-level modeling system. Hardware description language (HDL) code is generated for one or more of a plurality of high-level subsystems in a high-level design tagged by the user for HDL code generation. Previously generated HDL code may be reused instead of generating new HDL code for each subsystem tagged by the user for HDL code reuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.