Patent · US Expired

Process for the formation of a spatial chip arrangement and spatial chip arrangement

US7087442B2 · kind B2 · utility

7Cited by

49References

6Claims

0Family size

Assignee

Pac Tech—Packaging Technologies Gmbh · DE

Inventors

Hans-Hermann Oppermann · Berlin, DE
Elke Zakel · Falkensee, DE
Ghassem Azdasht · Berlin, DE
Paul Kasulke · Berlin, DE

Key dates

Filing date	Sep 24, 2001
Grant date	Aug 8, 2006
Priority date	—
Expiry date	Feb 9, 2022

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged transverse to the longitudinal extent of the carrier substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.