Edge arrangements for integrated circuit chips
US7087452B2 · kind B2 · utility
39Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Apr 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming microelectronic devices. This may include providing a wafer device having metallization layers, a plurality of integrated circuits and a channel area provided around each of the integrated circuits. Materials from within each channel area may be removed by etching or by laser to form an air gap around a perimeter of each integrated circuit. Each air gap may prevent cracking and/or delamination problems caused by a subsequent dicing of the wafer device by a wafer saw into a plurality of devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.