Method of making a vertical compound semiconductor field effect transistor device
US7087472B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Oct 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/871
Abstract
In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate region is then formed on the sidewalls and the bottom surface of the second trench. Source regions are formed on opposite sides of the trench structure. Localized gate contact regions couple individual doped gate regions together. Contacts are then formed to the localized gate contact regions, the source regions, and an opposing surface of the body of semiconductor material. The method provides a compound semiconductor vertical FET structure having enhanced blocking capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.