Method for fabricating trench capacitors for integrated semiconductor memories
US7087484B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | May 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0387
Abstract
In a method for fabricating trench capacitors, in particular for memory cells having at least one selection transistor for integrated semiconductor memories, a trench for the trench capacitor is formed. The trench has a lower trench region, in which the capacitor is disposed, and an upper trench region, in which an electrically conductive connection from an electrode of the capacitor to a diffusion zone of the selection transistor is disposed. The method reduces the number of process steps for the fabrication of memory cells and enables fabrication of buried collars in the storage capacitors with an insulation quality as required for the fabrication of very large-scale integrated memory cells (<300 nm trench diameter).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.