Forming an intermediate layer in interconnect joints and structures formed thereby
US7087521B2 · kind B2 · utility
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3References
36Claims
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Key dates
| Filing date | Nov 19, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Nov 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a microelectronic structure are described. Those methods include forming a first adhesion layer on a conductive layer, forming an intermediate layer on the first adhesion layer, and forming a barrier layer on the intermediate layer, wherein the intermediate layer includes a coefficient of thermal expansion that is approximately between the coefficient of thermal expansion of the first adhesion layer and the coefficient of thermal expansion of the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.