Method to fill the gap between coupled wafers
US7087538B2 · kind B2 · utility
218Cited by
58References
63Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Aug 16, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/906
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of the coupled wafers, and using a vacuum to aid in the dispersion of the material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.