Direct alignment scheme between multiple lithography layers
US7087943B2 · kind B2 · utility
1Cited by
15References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Jan 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/18
Abstract
A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.